1. Field of the Invention
Example embodiments of the present invention in general relate to a layout of metal-oxide semiconductor (MOS) transistors and methods of disposing MOS transistors during fabrication for use in a highly integrated semiconductor memory device.
2. Description of the Related Art
In general, volatile semiconductor memory devices such as a dynamic Random Access Memory (RAM) or static RAM etc. are mounted as the memory becomes higher in speed and higher integration increases. This is done in conformity with higher performance of electronic systems such as a personal computer, electronic communication appliances, etc.
Manufacturers of memory chips have been trying to dispose and manufacture memory cells so as to match a scaled-down critical dimension and functional circuits connected to the memory cells. Thus, techniques to dispose circuits in a functional circuit region, i.e., a cell core region, which is adjacent to a cell formation region where memory cells are being rapidly scaled-down in the existing technique becomes an important factor in determining a high integration level. In the functional circuit region, a core logic circuit such as a column decoder (which functions as an interface circuit for a drive of unit memory cell) may be installed. Thus, techniques to more efficiently dispose MOS transistors of a circuit within the functional circuit region, while taking account of size limitations and without lowering the functionality, is required for increasingly higher speed and highly integrated semiconductor memory devices.
Meanwhile, scale-down of given semiconductor devices is becoming increasingly advanced with the progress of semiconductor manufacturing technology. One factor heightening the scale-down is known as a shallow trench isolation (STI) technology. The STI technology is a device isolation process to operationally isolate semiconductor devices formed on a semiconductor substrate. A shallow trench may be formed between devices to isolate semiconductor devices, and an insulation layer such as an oxide layer is filled within the formed shallow trench to obtain a desired isolation effect.
Recent trends to improve high integration of semiconductor devices make an insulation function of the STI substantially useless. An operating characteristic of certain semiconductor devices, as a stress influence of the STI largely increases based on the high integration tendency, may be substantially varied. Given parameters associated with this operating characteristic, a mobility and threshold voltage of carriers within a MOS transistor, and influences from other secondary orders may be contained.
Semiconductor manufacturers have continuously been endeavoring to increase simulation precision depending on a given layout, modeling with such influences. To substantially reduce a mechanical influence based on a given layout, a more desirable layout of transistors may be required.
Until recently, to reduce a critical dimension (CD) variation of a gate of polysilicon material (hereinafter, referred to as ‘gate poly’) in manufacturing transistors isolated through STI, dummy gate poly patterns which were not relevant to device operation were formed in parallel, like gate poly patterns of a transistor used as an actual device. This will be shown in more detail FIG. 4.
FIG. 1 illustrates a plane structure of a conventional MOS transistor, with the structure that source, gate and drain may be disposed in a gate length direction. FIG. 2 illustrates a current characteristic based on a reduction of active region size SA when the MOS transistor of FIG. 1 is embodied as a PMOS transistor. In FIG. 2, a transverse axis indicates a threshold voltage and a longitudinal axis indicates a drain current. FIG. 3 is an equivalent circuit illustrating various connections of typical P-type MOS transistors, and FIG. 4 illustrates, as an example, a conventional plane layout on a semiconductor substrate. FIG. 5 is a sectional view taken along a line X-X′ of FIG. 4.
Referring to FIG. 4, a plurality of dummy gate poly patterns 20, 21, 22 and 23 disposed in parallel in a length direction are formed equally to respective widths and lengths of a plurality of gate poly patterns 2, 4, 6, 8 and 10 of P-type MOS transistors PM1-PM5. These correspond one by one to the transistors PM1-PM5 of FIG. 3, so as to reduce a critical dimension variation in a photolithography process. The dummy gate poly patterns 20, 21, 22 and 23 are not circuits for use in circuit operation, and do not exist on an active region on which source/drain regions 1, 3, 5 and 7 are formed. Rather, the dummy gate poly patterns 20-23 exist on the STI region.
In FIG. 4, the STI region may be divided into first, second and third regions ST1, ST2 and ST3 for convenience of explanation. The first and second regions ST1 and ST2 designate isolation regions, each existing on an upper part and a lower part of the active region of FIG.4. The third region ST3 designates an isolation region existing between the active regions.
With reference to the sectional view of FIG. 5, the dummy gate poly pattern 20 is formed on an upper part of the STI region ST3, such that a gate oxide layer GOX is interposed between the dummy gate poly pattern 20 and the STI region ST3.
In a conventional layout of MOS transistors as shown in FIG. 4, a CD variation of gate poly is reduced in a photolithography process. But, when a scale-down of the device is accelerated, a stress influence of STI increases at an even greater rate. This causes a change in the operating characteristic of the transistor device. In other words, a mechanical influence of STI adversely affects nodes N1 to node N4 in FIG. 3, and also adversely affects a VDD node of a power source voltage. For example, in comparing MOS transistor PM4 with MOS transistor PM5, a source edge part and a drain edge part of the MOS transistor PM5 is entirely in contact with a STI region in a transverse direction as shown, but only a drain edge part of MOS transistor PM4 is in contact with the STI region. Thus, mechanical influences in these two transistors PM4 and PM5 are different from each other.
Referring now to FIG. 2, when the transistor of FIG. 1 is a PMOS transistor, a size SA of the active region representing a length of the drain or source may be reduced. Thus, a current Ids between the drain and source increases as is shown in FIG. 2. On the contrary, in an NMOS transistor, the size SA of the active region is reduced; thus the current Ids between the drain and source is also reduced. Even if a desirable size for the operation of the transistor device can be obtained, the characteristics and operation of the PMOS and NMOS transistors is altered toward another characteristic and/or operation due to the stress of STI, as described above.
Accordingly, a modeling technique of the device should be varied and precise, and a technique to verify and reflect this flexibility and precision may need to be developed. The verification of electrical characteristics of MOS transistors (depending on the given circuit layout) has a limitation as to precision. Thus, a different layout may be required in an effort to substantially reduce mechanical influences caused by the STI process.
FIG. 6 is a block diagram illustrating a core of a conventional semiconductor memory device. As shown in FIG. 6, a semiconductor memory device such as DRAM includes a column selection line driver 400 to drive a column selection line CSL which is connected to a memory cell array 100. In the core block of the conventional semiconductor memory device, the Y-directional size of column selection line driver transistors DT1, DR2 and DT3 within the column selection line driver 400 is determined based on a unit pitch of a plurality of bit line sense amplifiers that individually correspond to, and are connected to, bit lines of the memory cell array 100. That is, for the layout of driver transistors in a conventional column decoder, there is a limitation that the transistors are to be installed within a range of a unit pitch of the sense amplifiers in the Y-direction. Thus, the size of the gate poly for the driver transistor is large in the X-direction of FIGS. 7 and 8, in order to obtain the required driving function.
FIG. 7 is a plane view illustrating one layout example of transistors within a CSL driver of FIG. 6 according to the conventional art, and FIG. 8 is a plane view illustrating another layout example of transistors within the CSL driver of FIG. 6 according to the conventional art.
Referring to FIG. 7, the size of NMOS and PMOS transistors in the Y direction is limited to a unit pitch of a given sense amplifier, and is extended in an X direction. Reference number 410 indicates an active region that is doped with an n-type impurity, and reference number 420 indicates an active region doped with a p-type impurity. A gate oxide layer is formed as an NMOS transistor, and a gate poly 430 formed on the n-type active region 410 is divided and disposed as a finger type of structure.
Also, a gate oxide layer is formed as a PMOS transistor, and the gate poly 440 formed on the p-type active region 420 is divided and disposed as a finger type structure. When the gate poly is formed in the finger type and corresponding fingers function as a gate electrode, transistors corresponding to the number of fingers share an active junction. In other words, a relatively large drive capability can be obtained within a given, determined size.
However, it is difficult to dispose the gate poly in a type of three or more fingers, which is why there is a limitation that the size of transistors be within a range of unit pitch of a bit line sense amplifier in a Y direction. That is, the size of the Y direction is limited, thus the size in the X direction should be extended to increase a drive capability.
Referring now to FIG. 8, gate polys 460 and 470 are shown, for use as power capacitance adjacent to a gate poly of finger type in an X direction. Additionally the gate polys 460, 470 are disposed with a uniform interval, and basically employ the layout of FIG. 7. FIG. 8 illustrates a plane structure which includes gate polys of a finger type in an edge space. The plane structure also includes transistors PCT1 and PCT2 for use as power capacitance, in an edge space as is shown. The size of the X, Y direction in FIG. 8 is equal to the size of X, Y direction of FIG. 7.
As described above with reference to FIGS. 7 and 8, the conventional layout of MOS transistors has a problem in that the size of the transistor increases in one direction. This adversely influences high integration of devices.